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Questions tagged [length-matching]

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Assume you want to route a LPDDR4 memory. You enter a situation were you cannot no longer proceed because there is a via blocking your path. So you decide to remove that via and route your trace. But ...
euraad's user avatar
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I wonder if it's OK to use serpentine routing between vias at under the BGA package. If you look at DDR0_DQ27, you can see that I using that area to perform length matching by use serpentine routing ...
euraad's user avatar
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Should bends be applied to mismatched differential tracks? Or should I avoid extra bends as long the differential track start as symetrical? In this case, my differential tracks are more than 0.1mm in ...
euraad's user avatar
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What is the maximum inter-lane skew length for RGMII 1000 Mbit/s? I'm looking at ST Microelectronics' Hardware Guidelines AN5489 for STM32MP SoC. It says that traces should be short with 'balanced ...
euraad's user avatar
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What is the maximum inter-lane skew length for DisplayPort 1.3? I'm looking at Texas Instruments Hardware Guidlines SPRACP4A for AM69 SoC. It says 1250 ps. Is that ...
euraad's user avatar
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I read a paper a while back describing that most group delay variation in RF systems is due to filters in them. (I have a reference if anyone might want that.) We even use filters as deliberate ...
Blue42's user avatar
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Is it a bad idea to route intra byte DQx on different layers? I am trying to interface AM6442 to LPDDR4 16bit. I have followed every constraint in TI's DDR layout guidelines to the letter, ...
Bubu's user avatar
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I have been told that trombones are much better to use than sawtooths, even if sawtooths may be prefered in some certians scenarios. Here I have added trombones to the differential pairs. If I had ...
euraad's user avatar
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1 vote
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Let's say that I have a point A and a point B. In between there must be a conductor. It must have a certain length. But I have to hang on to a pull-up resistor as well. But I can do that at point C. ...
euraad's user avatar
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What do we encounter if the impedance changes along the way? For example, what kind of problem can we encounter when one of the two complementary PCB's is 90 ohm and the other is 100 ohm? For example, ...
esat's user avatar
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4 votes
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I am tracing my first DDR2 with Cyclone V PCB and I can't find exact information about CLK vs DSQ vs ADR length matching. External Memory Interface Handbook Volume 2: Design Guidelines from Intel says ...
kornev.online's user avatar
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The following are the details of the wire I have: Nichrom 80, 32 Gauge (0.2744 mm diameter), measured resistance 6.84 ohms/foot or 22.44 ohms/m. I'm planning on powering this only via USB so my max ...
VisuaL HippocracY's user avatar
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I have designed an M2 adapter which converts from KeyE to KeyM. Practically this means my board can be inserted into a KeyE slot, and it can host a KeyM SSD. Gray rectangle is the KeyM socket on my ...
Daniel's user avatar
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I am currently researching the length matching problem in the PCB EDA domain and am curious as to why tools such as Allegro and Altium primarily use accordion, trombone, and sawtooth patterns to ...
David Lee's user avatar
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726 views

I'm using this KSZ8041MLLI device and this is its Hardware checklist I'm using the MII Interface between this PHY and the MAC Controller (STM32 MCU) on the same board. My question is whether we ...
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