SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.
SystemVerilog is a unified hardware description language (hdl) and verification language. Its two primary uses are to describe logical circuits targeted towards field-programmable gate arrays (FPGAs - fpga), programmable logic devices (PLD) and application-specific integrated circuits (ASICs) and to develop tests and environments to validate these circuit descriptions.
It is defined by IEEE 1800-2017 and with the exception of keywords, is a backwards-compatible superset of verilog, IEEE 1364-2005.
