Questions tagged [system-verilog]
SystemVerilog is a unified hardware design, specification, and verification language based on extensions to Verilog.
15 questions
3
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1
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SystemVerilog: LED blinker control logic
I built this simple blinker in SystemVerilog and would very much like some help to make it better:
control.sv
...
- 163
4
votes
1
answer
87
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I2C master interacting with ADC IC
The code is for an I2C master that interacts with an ADC IC (ADS1115).
Is there a more practical way of seeing what the internal regs and wires are doing in testbench, without creating a ports for ...
- 97
4
votes
1
answer
243
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I2C serial communication protocol for university project
For now, I have only implemented a simple I2C protocol where only the master transmits the data. Also there is ack_bit for the I2C Address only. For state 5, i.e.,...
7
votes
1
answer
273
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RISCV ALU Implementation in SystemVerilog
This will be first of many things I will submit during my journey of self (re)learning CPU design.
I have ALU implementation for RiscV base instruction. I am not fully sure what I am looking
for, but ...
- 937
3
votes
1
answer
231
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Implements a READ ID command between the iCE40 HX8K and the AT25SF0818 in Verilog
Question
How can I improve my Verilog code?
Context
Flash Read ID Operation
This project is an implimentation of the Read Manufacturer and Device ID (9Fh) operation ...
- 163
3
votes
1
answer
89
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Detect when X-axis inputs and Y-axis inputs go high
I am working on a module named PinCoordinates that detects when X-axis and Y-axis inputs go high. This will be programmed onto an Altera MAX V CPLD. I am ...
2
votes
1
answer
232
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ROM memory in SystemVerilog and cocotb
The Verilog module describes a ROM memory. An initialization file is needed for the INIT_FILE parameter.
Below are Makefile, gtkwave.tcl to launch gtkwave, ...
- 35
1
vote
1
answer
113
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Clock frequency meter module
The module measures input clocks. It requires some reference clock. There can be from one to five input clocks to measure it. Output values are usual unsigned ones. As expected, it should be reset ...
- 35
2
votes
1
answer
289
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SystemVerilog implementation of an N-bit prefix adder logic design
I want some feedback about my code (anything is welcome). It is working, but it feels like a clumsy implementation. Because I am self-learning from a book without an answers section, it becomes ...
4
votes
2
answers
611
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Simple GPIO design module in SystemVerilog
I am designing a very crude general-purpose input/output (GPIO) module to provide IO pin control to a RISC-V (like) architecture microprocessor I am currently playing with.
This is the code so far:
<...
- 41
3
votes
2
answers
1k
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Accessing multiple dynamic libraries with the same extern C methods
I have multiple pre-compiled dynamic libraries that use the same extern "C" function names. The functions can behave differently for each dynamic library. ...
- 523
1
vote
1
answer
181
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fixed pseudo-random binary sequence (prbs)
On recent comments based fixed modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by ...
- 453
4
votes
1
answer
361
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Heart beat RTL module
Heart rate or blink generator. Clocked from the system frequency, but calculated from a constant of 120MHz. Has a prescaler with values 2, 3, 5, 6, for even heart beat / blinking. The IS_DEBUG ...
- 453
2
votes
1
answer
2k
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pseudo-random binary sequence (prbs)
Modules for FPGAs for generating a pseudo-random bit sequence are presented. The first module generates a bit sequence. The third module speeds up the generation by transferring the bus to, for ...
- 453
6
votes
2
answers
2k
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Simple SystemVerilog AXI controller
I have a more long-term project I'm using to learn FPGA/HDL, and this is first sub-component of it used for testing. I'm targeting Zynq device.
I'd like to create a component which creates an image. ...
- 161