Abstract: A display device comprises a bank pattern disposed on a substrate and including a first bank pattern extended in a direction, second bank patterns adjacent to each other with the first bank pattern disposed between the second bank patterns, and connection portions connecting the first bank pattern with the second bank patterns, a first electrode disposed on the first bank pattern, a second electrode disposed on one of the second bank patterns, and a third electrode disposed on another one of the second bank patterns, an insulating layer disposed on the bank pattern, the first electrode, the second electrode, and the third electrode, and light emitting elements disposed between the first electrode and the second electrode, and between the first electrode and the third electrode.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first interlayer insulating film defining a lower wiring trench; a lower wiring structure including a first lower barrier film which extends along sidewalls of the lower wiring trench, and a lower filling film which is on the first lower barrier film; a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film defining an upper wiring trench which exposes at least part of the lower wiring structure; and an upper wiring structure provided in the upper wiring trench and connected to the lower wiring structure. An upper surface of the first lower barrier film is closer to a bottom surface of the lower wiring trench than each of an upper surface of the first interlayer insulating film and an upper surface the lower filling film. The upper surface of the first lower barrier film is concave.

Abstract: There is provided a copper bonding wire having an improved storage life in the atmosphere. There is specifically provided a copper bonding wire for semiconductor devices characterized in that a density of crystal grain boundary on a surface of the wire is 0.6 (?m/?m2) or more and 1.6 (?m/?m2) or less.

Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor layer, a micro-electromechanical systems (MEMS) structure defined in the semiconductor layer, a bond ring over the semiconductor layer, and a cap structure over the MEMS structure and bonded to the bond ring. The MEMS structure has an upper surface and the cap structure has a lower surface facing the upper surface of the MEMS structure. Dimples of eutectic material are on the upper surface of the MEMS structure.

Abstract: A semiconductor apparatus and a method for manufacturing the semiconductor apparatus are provided. The semiconductor apparatus includes: a base substrate; a chip arranged on the base substrate, wherein the chip includes a chip main body and a plurality of terminals arranged on the chip main body; a terminal expansion layer arranged on the base substrate, the terminal expansion layer including a conductive material, and the terminal expansion layer and at least one terminal are located on a same side of the chip main body; and a plurality of expansion wires in the terminal expansion layer, wherein the plurality of expansion wires are electrically connected to the plurality of terminals, respectively, to lead out the plurality of terminals, wherein an orthographic projection of at least one expansion wire on the base substrate completely covers an orthographic projection of a terminal electrically connected to the expansion wire on the base substrate.

Abstract: A semiconductor package capable of reducing or preventing cracks from occurring in a conductive bump and a method for manufacturing the same. The semiconductor package includes a semiconductor chip; a first conductive bump; a first re-distribution layer which is provided between the semiconductor chip and the first conductive bump and electrically connects the semiconductor chip and the first conductive bump; and a buffer structure which formed to fill up a space between a side surface of the first conductive bump and one surface of the first re-distribution layer, in which the buffer structure includes a plurality of pores.

Abstract: A transistor with an embedded insulating structure set includes a substrate. A gate is disposed on the substrate. A first lightly doped region is disposed at one side of the gate. A second lightly doped region is disposed at another side of the gate. The first lightly doped region and the second lightly doped region have the same conductive type. The first lightly doped region is symmetrical to the second lightly doped region. A first source/drain doped region is disposed within the first lightly doped region. A second source/drain doped region is disposed within the second lightly doped region. A first insulating structure set is disposed within the first lightly doped region and the first source/drain doped region. The first insulating structure set includes an insulating block embedded within the substrate. A sidewall of the insulating block contacts the gate dielectric layer.

Abstract: Device structures with an isolation well and methods of forming a device structure with an isolation well. The structure comprises a first well of a first conductivity type in a semiconductor substrate, and a second well of a second conductivity type in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. The first well includes a plurality of segments, and the second well is positioned in a vertical direction between the segments of the first well and a top surface of the semiconductor substrate.

Abstract: An electronic package, in which a heat dissipation structure is disposed on a carrier structure to form a packaging space for electronic components to be accommodated in the packaging space, and the electronic components are completely encapsulated by a heat dissipation material to prevent the electronic components exposing from the heat dissipation material so as to improve the heat dissipation effect.

Abstract: An apparatus for manufacturing a bonded semiconductor structure includes a wafer processing unit including a first and second bonding chambers; a wafer transfer module including a first chamber coupled to the first and second bonding chambers, wherein the wafer transfer module is configured to transport a wafer within the first chamber and into and out of the wafer processing unit; a die transfer module including a second chamber coupled to the first and second bonding chambers, wherein the die transfer module is configured to transport a die carrier within the second chamber and into and out of the wafer processing unit; and a control system configured to control conditions of the first bonding chamber, the second bonding chamber, the first chamber and the second chamber. The first bonding chamber, the second bonding chamber, the first chamber and the second chamber are under same conditions controlled by the control system.

Abstract: The present disclosure relates to a method of manufacturing a semiconductor light emitting device, the method comprising: providing a growth substrate on which a first semiconductor region, an active region and a second semiconductor region are sequentially formed; bonding a first light transmitting substrate to the second semiconductor region; removing the growth substrate from the first semiconductor region; attaching a second light transmitting substrate through an adhesive layer to the first semiconductor region from which the growth substrate is removed; laser ablating the first light transmitting substrate from the second semiconductor region; exposing part of the first semiconductor region, and forming a first flip chip electrode and a second flip chip electrode on the exposed first semiconductor region and the exposed second semiconductor region, respectively.

Abstract: An example apparatus includes: an integrated circuit including a first surface and terminals; a package including: a housing around the integrated circuit, the housing exposing the first surface; and an electrical interconnect including a second surface and an opening, the second surface electrically coupled to the terminals, the second surface mechanically coupled to the housing, the opening configured to expose the first surface.

Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a chamber on which a substrate is placed, a first gas flow path configured to supply a first processing gas into the chamber, a second gas flow path configured to supply a second processing gas into the chamber, a first replacement gas flow path configured to supply a first replacement gas into the chamber, a replacement gas heating unit configured to heat the first replacement gas, a second replacement gas flow path configured to supply a second replacement gas into the chamber, and a replacement gas cooling unit configured to cool the second replacement gas.

Abstract: A display device and a manufacturing method of a display device are provided. The display device includes a substrate including a pixel defined thereon; a light emitting diode disposed in the pixel; an insulating layer covering the light emitting diode; a light collecting structure on at least a part of the insulating layer; and a reflective layer disposed at a side surface of the light collecting structure. The side surface of the light collecting structure may have a reverse tapered shape.

Abstract: A device includes a semiconductor chip and a redistribution layer (RDL) structure connected to the semiconductor chip. The redistribution layer structure comprises a first region including: a first bump connected to the semiconductor chip; a second bump; and a plurality of first redistribution layers connected between the first bump and the second bump. The RDL structure includes a second region laterally surrounding the first region, the second region including a plurality of second redistribution layers. The RDL structure includes an isolation region laterally separating the plurality of first redistribution layers from the plurality of second redistribution layer. The isolation region includes at least one region that is straight, continuous, extends from an upper surface of the redistribution layer structure to a lower surface of the first redistribution layer structure, and has at least a selected width.

Abstract: Spacer layers on sidewalls of a dummy gate structure included in a semiconductor device are trimmed or etched prior to or during a replacement gate process in which the dummy gate structure is replaced with a replacement gate structure. A radical surface treatment operation is performed to etch the spacer layers, which is a type of plasma treatment in which radicals are generated using a plasma. The radicals in the plasma are used to etch the spacer layers such that the shape and/or the geometry of the remaining portions of the spacer layers reduces, minimizes, and/or prevents the likelihood of an antenna defect being formed in the spacer layers and/or in a work function metal layer of the replacement gate structure. This reduces, minimizes, and/or prevents the likelihood of occurrence of damage and/or defects in the replacement gate structure in subsequent processing operations for the semiconductor device.

Abstract: A semiconductor device includes a substrate, a first transistor disposed on the substrate, a second transistor in proximity to the first transistor on the substrate, at least one interlayer dielectric layer covering the first transistor and the second transistor, a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor.

Abstract: A lead frame includes: leads; and a dambar arranged between the leads and connecting the leads to each other, wherein each of the leads includes: a lower lead groove formed in a first surface for a wettable flank structure; and an upper lead groove formed in a second surface opposite the first surface and aligned with the lower lead groove in a thickness direction, wherein in a sawing process, a portion of the lead between the lower lead groove and the upper lead groove is at least partially removed.

Abstract: A lead frame includes a die pad, a plurality of leads, at least one support lead, and a frame member. The frame member includes two first connection bars and two second connection bars. The plurality of leads include a plurality of specific leads. The plurality of specific leads are each connected to the first connection bar. At least one of the specific leads is connected to the second connection bar via the at least one support lead. The cross-sectional second-order moment of a cross section of the at least one support lead perpendicular to a Y direction around an X axis is equal to or more than the cross-sectional second-order moment of a cross section of the at least one support lead perpendicular to an X direction around a Y axis.