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Insights: pConst/basic_verilog
Overview
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- 0 Merged pull requests
- 1 Open pull request
- 0 Closed issues
- 1 New issue
There hasn’t been any commit activity on pConst/basic_verilog in the last week.
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1 Pull request opened by 1 person
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Fix undefined `clk_div` in `freq_meter.sv`
#7 opened
Jul 25, 2025
1 Issue opened by 1 person
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`readout_valid` Signal Always Stuck at Zero in `freq_meter`
#6 opened
Jul 25, 2025
1 Unresolved conversation
Sometimes conversations happen on old items that aren’t yet closed. Here is a list of all the Issues and Pull Requests with unresolved conversations.
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Clarify non-reset behavior of Gray counter in `cdc_strobe` for ASIC compatibility
#3 commented on
Jul 25, 2025 • 0 new comments