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I’m using an EEPROM where a Write control pin is present. If it is driven low, write operations are enabled. I want to keep it in low state all the time.

However in some applications I’ve seen a 10k pull down resistor being used instead of directly pulling it to ground. Why is it so? Would like to have some reference on this

Datasheet link

https://www.st.com/content/ccc/resource/technical/document/datasheet/group0/cb/91/ba/7d/0b/c1/4d/f6/CD00147128/files/CD00147128.pdf/jcr:content/translations/en.CD00147128.pdf

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  • \$\begingroup\$ What are you trying to achieve by switching the EEPROM's A1 & A2 inputs to 3.3V? You cannot simply leave thee inputs floating when are not switch-switched to 3.3v. CMOS inputs must never be left floating, unless they have an internal pull-up or pull-down resistor. Doing so will cause erratic behavior of the IC and will likely cause the IC to draw an inordinate amount of current, which itself may cause other problems. \$\endgroup\$ Commented Nov 24 at 19:03
  • \$\begingroup\$ @WoodrowBonewright That's exactly why they are left unconnected. Datasheet says they read as low when left unconnected. Datasheet also says they must be connected to Vcc or Vss, so it's quite contradictory. \$\endgroup\$ Commented Nov 24 at 20:57
  • \$\begingroup\$ @glibcrossroads, I don't know how much experience you have with circuit design, but I'll offer a word of advice. This IC has been made by a few manufacturers over the past decade or so it's been available. The A1-A2 PD characteristics stated in the ST data sheet may not be true for 24M01s of other brands. It also wouldn't be the first time a data sheet stated an incorrect characteristic. There is an easy way to check the presence of internal PD resistors. With the chip operating connect a 10K or 50K pot (wiper and CW) in series with the input and Vcc, while monitoring the voltage on the pin. \$\endgroup\$ Commented Nov 25 at 11:35
  • \$\begingroup\$ @glibcrossroads, Adjust the pot slowly from the highest resistance to the lowest resistance while observing the pin voltage. Theoretically, when the pin voltage gets to 50% of Vcc, the pot resistance will equal the internal PD resistance. Measure the pot (wiper to CW) with an Ohmmeter for the answer. If the pin voltage jumps to Vcc while attempting this test, there's no internal pull-up. Again, if you are not using the ST brand part, be wary. Check the data sheet for other brands to see what they state for their A1-A2 PD capabilities too. \$\endgroup\$ Commented Nov 25 at 11:42

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However in some applications I’ve seen a 10k pull down resistor being used i

Might be! I bet in these applications, the designer wanted the option to drive things high later on.

In your case, the datasheet even has an example circuit where the ~WC pin is simply tied to GND.

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There are different people doing thing with different memory chips.

This chip specifically allows the write protection pin to float unconnected, as it has an internal pull-down.

So this chip does not care if the pin is left unconnected, has a resistor to ground, or a direct connection to ground.

Some other similar chips may be different in this regard.

In a noisy environment, it might be best to directly wire to ground to avoid problems, and a separate resistor is stronger than no resistor at all, and allows the flexibility to change the resistor value or prototyping some wires to cause write protect to be enabled while testing and validating the software what it does if it encounters errors.

So there's many reasons why to put a resistor, why to leave it out, or why to put some specific or any value of resistance, including a 0R jumper resistor.

On a side note, I don't know how long your bus is, but the worst thing to do is to put SDA and SCL right next to each other, and your design seems to do that. The GPIO might also couple to your SCL. It's just best to not do that but have some shielding like supply or ground wires between SDA and SCL and other wires.

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